The invention relates to a semiconductor device having at least one pair of complementary insulated gate field effect transistors and having a semiconductor body with a highly doped substrate of a first conductivity type, a less highly doped epitaxial layer of the first conductivity type disposed on it and adjoining a surface of the body and a first region of the second opposite conductivity type, which also adjoins the surface and is entirely surrounded within the semiconductor body by the epitaxial layer, source and drain zones of the first conductivity type of a first insulated gate field effect transistor being provided within the first region and source and drain zones of the second conductivity type of a second insulated gate field effect transistor being provided beside the first region, of which the source zone is located between the drain zone and the first region, while a second region of the second conductivity type is provided below the source zone of the second field effect transistor.
A semiconductor device of the kind described above is known from the published European Patent Application No. EP 138162.
Integrated monolithic circuits comprising complementary insulated gate field effect transistors, generally designated as CMOS circuits, are used frequently and for many applications.
In given circumstances, more particularly in the presence of an inductive load, one or more pn junctions inherent in the semiconductor structure and connected under normal operating conditions in the reverse direction can become connected in the forward direction and can convey current. This gives rise to dissipation and in certain cases, especially in circuits having a high packing density, to "latch-up", i.e. to the ignition of parasitic pnpn ("thyristor") structures, which afterwards cannot be switched off or can be switched off only with difficulty, which may even lead to irrepairable damage of the device.
Attempts can be made to avoid these effects by disposing the various semiconductor zones farther away from each other and by thus increasing the resistance of the various current paths and reducing the possibility of parasitic thyristor effect. However, the advantage of a high packing density is thus lost.
The European Patent Application No. EP 138162 discloses a semiconductor device comprising complementary field effect transistors, in which, in order to counteract the aforementioned "latch-up" effect, a highly doped layer-shaped buried lattice is provided under the whole CMOS structure, which lattice is in contact with and has the same conductivity type as the "first" region.